1. Field of the Invention
The present invention relates to a VITERBI decoder used for error correction in such equipment as a digital mobile communication terminal which is required to be more compact and faster in processing.
2. Description of the Prior Art
FIG. 1 is a block diagram of a VITERBI decoder, in which indicated by 1 is a data input port, 2 is a computation unit which implements the computation for the path and metric, 3 is a metric memory capable of revising the path-metric, 4 is a decoded data delivery port, 5 is a path memory which stores path selecting information, and 6 is a controller which controls the data input port 1, computation unit 2, metric memory 3, and other functional blocks. Indicated by 7 is external input data, 8 is input data processed by the data input port 1 and delivered to the computation unit 2, 9 is a control signal, 10 is a path-metric of the past which is read out of the metric memory 3 and delivered to the computation unit 2, 11 is a new path-metric which is read out of the computation unit 2 and written to the metric memory 3, 12 is path selecting information which is provided by the computation unit 2 and written to the path memory 5, and 13 is decoded data which is taken out of the decoded data output port 4 and delivered to the outside.
FIG. 2 is a block diagram showing the computation unit 2, in which the same or equivalent portions as in FIG. 1 are referred to by the common symbols. Indicated by 14a and 14b are branch metric computation circuits, 15a and 15b are path-metric computation circuits, 16 is a metric comparison circuit which compares two path-metrics, and 17 is a path selection circuit which selects one of two path-metrics based on the path selecting information 12 provided by the metric comparison circuit 16.
Next, the operation will be explained.
In the VITERBI decoder shown in FIG. 1, the metric memory 3 and path memory 5 are initialized at the beginning. When a symbol in the input data 7 is entered to the data input port 1, the data input port 1 introduces the symbol in response to the timing signal included in the control signal. The data input port 1 holds the symbol until the computation unit 2 completes the computations for all branches.
The computation unit 2 operates in accordance with the control signal 9 provided by the controller 6. Namely, the computation unit 2 bases its operation on the VITERBI algorithm in implementing the computation of metric and path for the path-metric 10 of the past read out of the metric memory 3 and the control signal 9. A resulting new path-metric 11 and path selecting information 12 are stored in the metric memory 3 and path memory 5, respectively. The decoded data 13 is delivered through the decoded data output port 4 based on the contents of the path memory 5.
Next, the operation of the computation unit 2 shown in FIG. 2 will be explained. The branch metric computation circuits 14a and 14b calculate the branch metric for the input symbol in accordance with the control signal 9. Specifically, the branch metric computation circuit 14a calculates the branch metric of one branch (an immediate branch indicated by the control signal 9) for a symbol in the input data 8. The branch metric computation circuit 14b calculates the branch metric of another branch (indicated by the control signal 9) for an immediate symbol.
Subsequently, the path-metric computation circuits 15a and 15b calculate new path-metrics based on the calculated branch metrics and each path-metric 10 of the past corresponding to each branch read out of the metric memory 3. Specifically, the path-metric computation circuit 15a sums the path-metric 10 (read out of the metric memory 3 in accordance with the control signal 9 from the controller 6) corresponding to the start point of the branches which have been treated in the computation by the branch metric computation circuit 14a and the branch metric calculated by the branch metric computation circuit 14a thereby to evaluate a new path-metric. The path-metric computation circuit 15b sums the path-metric 10 corresponding to the start point of the branches which have been treated in the computation by the branch metric computation circuit 14b and the branch metric calculated by the branch metric computation circuit 14b thereby to evaluate a new path-metric. The computations of the above-mentioned two path-metrics are carried out for each status on the Trellis diagram (i.e., possible states of the decoder) at a time point after the immediate entry of the symbol The controller 6 issues the control signal 9, indicative of the computation of the two branches in the states after the entry of symbol on the Trellis diagram, to the metric computation circuits 14a and 14b.
Subsequently, the metric comparison circuit 16 compares the two path-metrics, and produces the path selecting information 12 based on the result of computation. A path selection circuit 17 selects a path-metric depending on the path selecting information 12, i.e., the smaller path-metric, and delivers it as a new path-metric 11. This selection process takes place for all possible states of the decoder.
The conventional VITERBI decoder arranged as described above is intricate in circuit configuration and therefore unsuitable for size reduction, and in addition it is difficult to speed up the process due to cumulative process times expended by individual circuits. Moreover, the content of computation is dependent on each circuit, and it cannot easily cope with a change in computation. The technique which resembles the foregoing conventional VITERBI decoder is described in the above-mentioned U.S. Pat. No. 4,583,078.